One of the metrics employed in designing a clocking architecture is skew (i.e., phase mismatch). A clocking architecture may suffer from process, voltage and temperature mismatch, even along identical paths.
Process variation is the naturally occurring variation in component attributes (e.g., length, width, oxide thickness) when integrated circuits are fabricated. The amount of process variation becomes pronounced at smaller process nodes as the variation becomes a larger percentage of the full length or width of the device. Process variation causes measurable and predictable variance in the output performance of all circuits due to mismatch. If the variance causes the measured or simulated performance of a particular output metric (bandwidth, gain, rise time, etc.) to fall below or to rise above the specification for the particular circuit or device, it reduces the overall yield for that set of devices.
Voltage and temperature gradients may cause timing variation in a chip. For example, thermal hot spots may be created in a system which in turn can increase in voltage drop. Similarly, the current flowing through the interconnections can generate heat, which in turn can affect the temperature gradients. Additionally, die temperature may not be uniform or consistent across different chips.
A clocking architecture may use a feedback-loop clock deskew (i.e., phase match) schemes to align clock phases at discontinuities in clock trees. One method of reducing clock skew is by using a closed loop feedback system where delay-locked loop (DLLs) and interfaces between the clock skew boundaries feed the DLLs different phases of the clocks at a given boundary. That information is then fed back to delay elements in order to match the delays at the inputs to the DLL. However, the problem with this technique is that the system requires a user mode clock to be continuously running to operate correctly. Any stoppage of the clock for purposes of clock gating, or switching over to another clock will cause the system to lose lock.